This invention relates to devices that may be used to implement a digital-information handling system that operates at gigabits per second rates (i.e., each bit occupies only a small fraction of a nanosecond) and, more particularly, to such devices that employ microwave phase logic (MPL) for this purpose.
Known approaches to binary encoding include (1) DC amplitude pulse (a binary "1" is represented by a first given voltage level and a a binary "0" is represented by a second given voltage level, which first and second given voltage levels may have either the same or different polarities depending on the standard logic family employed, one of the voltage levels may be zero); (2) RF pulse (a binary "1" is represented by an RF carrier modulated by a first given amplitude and a binary "0" is represented by an RF carrier modulated by a second given amplitude, wherein one of the two amplitudes may or may not be zero), and (3) biphase (both a binary "1", a binary "0" and a reference are all represented by the same RF carrier frequency of a certain amplitude with a specified one of the binary "1" and binary "0" being in-phase with the phase of the reference and the other of the binary "1" and binary "0" being 180.degree. out-of-phase with the phase of the reference).
As is known, any of these three binary encoding approaches may be converted to one of the others. For instance, DC amplitude pulse encoding may be converted to RF pulse encoding by amplitude modulation and RF pulse encoding may be converted to DC amplitude pulse encoding by either envelope detection or heterodyning techniques. RF pulse encoding may be converted to biphase encoding by comparing it to an RF carrier which has the same frequency as it, is 180.degree. out-of-and has an amplitude in between the first and second given amplitudes of it. Similarly, biphase encoding may be converted to RF pulse encoding by combining it with an RF carrier which has the same frequency as it, is in-phase with the phase representing a binary "1", and has a specified given amplitude no greater than the amplitude of the biphase coded signal.
In a digital-information handling system employing either DC amplitude pulse and RF pulse binary encoding is non-continuous in that it involves a switching time between successive bits during which the binary state represented by them may be changed. Therefore, logic devices employing DC amplitude pulse and RF pulse binary encoding for a baseband digital-information handling system, starting at or near DC and extending to microwave with a multi-gigahertz bandwidth would be very difficult to design. However, a multi-gigahertz bandwidth would be a moderate percentage of a relatively high continuous microwave carrier frequency (e.g., 16 GHz) that employs biphase coding.
The general idea of certain types of logic devices that make use of Microwave Phase Logic.(MPL) and are capable of being implemented by means of devices responsive to biphase-coded signals applied thereto, have been known for many years. As is known, MPL devices makes use of the relationship of the respective phases of one or more biphase-coded input signals relative to the phase of a reference signal to determine the phase of one or more biphase-coded output signals relative to the phase of the reference signal. Included among known MPL devices are NOT gates, AND gates, OR gates, NAND gates, NOR gates, full adders, comparators, etc. In addition, because it is essential that the respective amplitudes of biphase-coded signals and reference signal have one or more certain specified levels, it is known to employ limiting amplifiers as MPL devices to achieve and maintain these specified levels.
However, prior to the present invention, none of these certain types of MPL devices could be implemented by means of cost-effective, minature-sized, multigate digital microwave-monolithic-integrated-circuit (MMIC) field-effect transistors (FET) that operate at gigabit/second speed. Further, the present invention makes it possible for the first time to implement several other types of MPL logic devices that incorporate doubly balanced mixers operating at gigabit/second speeds. Doubly balanced mixers suitable for operation at gigabit/second speeds, per se, are part of the prior art and are described in some detail on pages 269-288 of the book entitled "Microwave Mixers", Second Edition, by Stephen A. Maas, published in 1993 by Artech House, Inc. Although limiting amplifiers employed as MPL devices operating at gigabit/second speeds may be implemented by means other than doubly balanced mixers, doubly balanced mixers are to be preferred.